The subject invention generally relates to phase locked loop circuits, and is directed more particularly to track and hold phase locked loop circuitry which includes circuitry for tracking a reference signal and circuitry for holding a sample of the reference to provide for more accurate operation at high sample rates.
Phase locked loop circuits are utilized in data tape drives and disk drives to recover clock information for reading data from the data storage medium. Such clock information is not explicitly written for each bit recorded to tape. Typically, the data bits are written to tape at predetermined data bit intervals with a binary 1 being written to tape pursuant to a transition in the write current level which causes a flux reversal, while a binary 0 is "written" by no transition in the write current level. The technique of representing binary 1's by transitions has been utilized for various known factors including the desire to reduce the number of flux reversals required to write data to tape.
The premise of utilizing the foregoing technique is that data bits are supposed to be written at equally spaced intervals on tape, physically and in time. Thus, data is written to tape by providing appropriate transition/no transition write signals at predetermined intervals. Data is read from tape by timing the output into predetermined intervals and detecting the presence or absence of a transition during each of such intervals. If tape speed were capable of being constant, reading data would be a matter of synchronizing the output to a fixed clock. However, tape speed variations are inevitable, and phase locked loop circuitry is commonly utilized to track tape speed for reading. Simply stated, 1's are readily detected and the problem is to determine the number of any intervening 0's.
In order to provide a phase locked loop having a bandwidth that is independent of the data pattern read from the tape, phase locked loop circuitry having a sample and hold type phase comparator is generally preferred. An example of a PLL having a digital sample and hold type phase comparator is disclosed in commonly assigned U.S. Pat. No. 4,644,420. The digital phase comparator disclosed therein utilizes a voltage controlled oscillator running at 32 times the data rate, in accordance with the generally accepted understanding as to digital phase comparators that the VCO must run at a relatively high multiple of the data rate in order to achieve sufficient accuracy.
A consideration with a digital implementation such as that referenced above is that higher VCO frequencies are needed with increased data rates. For example, at a read clock rate of 9.3 MHz, a VCO center frequency of about 150 MHz would be required, which would be pushing the limits of existing Large Scale Integrated (LSI) circuit technologies.
Known sample and hold type analog phase comparators typically require the sampling of a ramp voltage, and considerations with such analog phase comparators include the time required to discharge the ramp, which reduces the useful timing window since sampled information is not valid during such ramp discharge time. A further consideration is the time required to change the voltage on the sampling capacitor to a new voltage from the previous "hold" voltage, which requires that the sample pulse have a finite width. If the sample time overlaps the ramp discharge time of the ramp, the sample will be indeterminate. Thus, the useful timing window is also reduced by the width of the sample pulse. At higher read clock rates, the timing window reductions produced by the ramp discharge time and the sample time can be significant in comparison to the time domain data bit interval (i.e., the interval for one data bit).